ph1lw21 Welcome to the forum, you are the first ! 👍
Thanks for you feedback and reviewing the schematic of the v.1.0 of the board I think that I have done a huge mistake with the position of the pins in the JP1.
In fact, if you bridge the LLC pin (= pin 3) with the data pin (=pin 2) as reported in the documentation (config B), the D2 pin of the MCU that carries the signal is completely excluded from the logic level converter circuit and this is no good!
I have to retest the board bridging pin 1 and 3, maybe in this way the LLC circuit can work.